SI8416DB www.vishay.com vishay siliconix s15-0932-rev. b, 20-apr-15 1 document number: 63716 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 n-channel 8 v (d-s) mosfet marking code: xxxx = 8416 ? xxx = date / lot traceability code ordering information: ? SI8416DB-t2-e1 (lead (pb)-free and halogen-free) features ? trenchfet ? power mosfet ? ultra-small 1.5 mm x 1 mm maximum outline ? ultra-thin 0.59 mm maximum height ? material categorization: ? for definitions of co mpliance please see www.vishay.com/doc?99912 applications ? low on-resistance load switch for portable devices ? - low power consumption, ? low voltage drop ? - increased battery life ? - space saving on pcb notes a. surface mounted on 1" x 1" fr4 board. b. t = 10 s. c. refer to ipc/jedec ? (j-std-020), no manua l or hand soldering. d. case in defined as the top surface of the package. e. t c = 25 c package limited. f. maximum under steady stat e conditions is 85 c/w. g. case is defined as top surface of the package. product summary v ds (v) r ds(on) ( ? ) max. i d (a) d q g (typ.) 8 0.023 at v gs = 4.5 v 16 17 nc 0.025 at v gs = 2.5 v 16 0.030 at v gs = 1.8 v 16 0.040 at v gs = 1.5 v 15 0.095 at v gs = 1.2 v 3 micro foot ? 1.5 x 1 back s ide view 1 1 mm 1.5 mm xxxx xxx bump s ide view 5 d 6 s 1 g d 4 s 3 s 2 n-channel mosfet g d s absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 8 v gate-source voltage v gs 5 continuous drain current (t j = 150 c) t c = 25 c i d 16 e a t c = 70 c 16 e t a = 25 c 9.3 a, b t a = 70 c 7.4 a, b pulsed drain current (t = 300 s) i dm 20 continuous source-drain diode current t c = 25 c i s 11 t a = 25 c 2.3 a, b maximum power dissipation t c = 25 c p d 13 w t c = 70 c 8.4 t a = 25 c 2.77 a, b t a = 70 c 1.77 a, b operating junction and storage temperature range t j , t stg -55 to +150 c package reflow conditions c ir/convection 260 thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a, f r thja 37 45 c/w maximum junction-to-case (drain) g steady state r thjc 79.5
SI8416DB www.vishay.com vishay siliconix s15-0932-rev. b, 20-apr-15 2 document number: 63716 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. guaranteed by design, not subj ect to production testing. ? ? ? stresses beyond those listed under absolute maximum ratings ma y cause permanent damage to th e device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those in dicated in the operational sectio ns of the specifications is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0, i d = 250 a 8 - - v v ds temperature coefficient ? v ds /t j i d = 250 a -2.2- mv/c v gs(th) temperature coefficient ? v gs(th) /t j --2.7- gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 0.35 - 0.80 v gate-source leakage i gss v ds = 0 v, v gs = 5 v - - 100 na zero gate voltage drain current i dss v ds = 8 v, v gs = 0 v - - 1 a v ds = 8 v, v gs = 0 v, t j = 70 c - - 10 on-state drain current a i d(on) v ds ? 5 v, v gs = 4.5 v 5 - - a drain-source on-s tate resistance a r ds(on) v gs = 4.5 v, i d = 1.5 a - 0.019 0.023 ? v gs = 2.5 v, i d = 1 a - 0.021 0.025 v gs = 1.8 v, i d = 1 a - 0.023 0.030 v gs = 1.5 v, i d = 0.5 a - 0.027 0.040 v gs = 1.2 v, i d = 0.5 a - 0.040 0.095 forward transconductance a g fs v ds = 4 v, i d = 1.5 a - 22 - s dynamic b input capacitance c iss v ds = 4 v, v gs = 0 v, f = 1 mhz - 1470 - pf output capacitance c oss - 580 - reverse transfer capacitance c rss - 450 - total gate charge q g v ds = 4 v, v gs = 4.5 v, i d = 1.5 a -1726 nc gate-source charge q gs -1.8- gate-drain charge q gd -3.4- gate resistance rg v gs = 0.1 v, f = 1 mhz - 2.5 - ? turn-on delay time t d(on) v dd = 4 v, r l = 2.7 ? i d ? 1.5 a, v gen = 4.5 v, r g = 1 ? -1325 ns rise time t r -1530 turn-off delay time t d(off) -4080 fall time t f -1020 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c - - 20 a pulse diode forward current i sm --20 body diode voltage v sd i s = 1.5 a, v gs = 0 - 0.7 1.2 v body diode reverse recovery time t rr i f = 1.5 a, di/dt = 100 a/s, t j = 25 c -3570ns body diode reverse recovery charge q rr -1835nc reverse recovery fall time t a -13- ns reverse recovery rise time t b -22-
SI8416DB www.vishay.com vishay siliconix s15-0932-rev. b, 20-apr-15 3 document number: 63716 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) output characteristics on-resistance vs. drain current and gate voltage gate charge transfer characteristics capacitance on-resistance vs. junction temperature 0 5 10 15 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 i d - drain current (a) v d s - drain-to- s ource voltage (v) v gs = 5 v thru 1.5 v v gs = 1 v 0.00 0.02 0.04 0.06 0.08 0.10 0 4 8 12 16 20 r d s (on) - on-re s i s tance () i d - drain current (a) v gs = 1.2 v v gs = 1.5 v v gs = 2.5 v v gs = 4.5 v v gs = 1.8 v 0 1 2 3 4 5 0 4 8 12 16 20 v gs - g ate-to- s ource voltage (v) q g - total g ate charge (nc) v d s = 6.4 v v d s = 2 v v d s = 4 v i d = 1.5 a 0 2 4 6 8 10 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 i d - drain current (a) v gs - g ate-to- s ource voltage (v) t c = 25 c t c = 125 c t c = - 55 c 0 400 800 1200 1600 2000 2400 0 2 4 6 8 c - capacitance (pf) v d s - drain-to- s ource voltage (v) c i ss c o ss c r ss 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 - 50 - 25 0 25 50 75 100 125 150 r d s (on) - on-re s i s tance (normalized) t j - junction temperature ( c) v gs = 4.5 v, 2.5 v, 1.8 v; i d = 1.5 a v gs = 1.5 v; i d = 0.5 a v gs = 1.2 v; i d = 0.5 a
SI8416DB www.vishay.com vishay siliconix s15-0932-rev. b, 20-apr-15 4 document number: 63716 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) source-drain diode forward voltage threshold voltage on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient safe operating area, junction-to-ambient 0.1 1 10 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 i s - s ource current (a) v s d - s ource-to-drain voltage (v) t j = 150 c t j = 25 c 0.2 0.3 0.4 0.5 0.6 0.7 0.8 - 50 - 25 0 25 50 75 100 125 150 v gs (th) (v) t j - temperature ( c) i d = 250 a 0.00 0.02 0.04 0.06 0.08 0.10 012345 r d s (on) - on-re s i s tance () v gs - g ate-to- s ource voltage (v) t j = 125 c t j = 25 c i d = 1.5 a 0 5 10 15 20 25 30 power (w) pul s e ( s ) 10 1000 0.1 0.01 0.001 100 1 0.01 0.1 1 10 100 0.1 1 10 100 i d - drain current (a) v d s - drain-to- s ource voltage (v) * v gs > minimum v gs at which r d s (on) i s s pecified 10 s 100 s 100 m s limited by r d s (on) * 1 m s t a = 25 c bvd ss limited 10 m s 1 s dc
SI8416DB www.vishay.com vishay siliconix s15-0932-rev. b, 20-apr-15 5 document number: 63716 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) current derating* power derating ? ? ? ? * the power dissipation p d is based on t j (max.) = 150 c, using junction-to-case thermal resistance, and is more useful in settling the upper dissi pation limit for cases where additional heatsinking is used. it is used to determine the current rating , when this rating falls below the package limit. 0 4 8 12 16 20 24 0 25 50 75 100 125 150 i d - drain current (a) t c - ambient temperature ( c) package limited 0 3 6 9 12 15 25 50 75 100 125 150 t c - ca s e temperature (c) power di ss ipation (w)
SI8416DB www.vishay.com vishay siliconix s15-0932-rev. b, 20-apr-15 6 document number: 63716 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) normalized thermal transient impedance, junction-to-ambient normalized thermal transient impedance, junction-to-case ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?63716 . 10 -3 10 -2 0 0 0 1 0 1 1 10 -1 10 -4 100 0.2 0.1 sq uare wave pul s e duration ( s ) normalized effective tran s ient thermal impedance 1 0.1 0.01 t 1 t 2 note s : p dm 1. duty cycle, d = 2. per unit ba s e = r thja = 85 c/w 3. t jm - t a = p dm z thja (t) t 1 t 2 4. s urface mounted duty cycle = 0.5 s ingle pul s e 0.02 0.05 10 -3 10 -2 10 -1 10 -4 1 0.1 0.2 0.1 duty cycle = 0.5 sq uare wave pul s e duration ( s ) normalized effective tran s ient thermal impedance 0.02 0.05 s ingle pul s e
package information www.vishay.com vishay siliconix revison: 20-apr-15 1 document number: 69426 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 micro foot ? : 6-bump (1.5 mm x 1 mm, 0.5 mm pitch, 0.250 mm bump height) notes (unless otherwise specified) 1. six (6) solder bumps are 95.5/3.8/0.7 sn/ag/cu. 2. backside surface is coated with a ti/ni/ag layer. 3. non-solder mask defi ned copper landing pad. 4. laser marks on the silicon die back. 5. b1 is the diameter of the solderable substrate surface, defi ned by an opening in the solder resist layer solder mask define d. 6. ? is the location of pin 1 note ? use millimeters as the primary measurement. dim. millimeters inches min. nom. max. min. nom. max. a 0.510 0.575 0.590 0.0201 0.0226 0.0232 a 1 0.220 0.250 0.280 0.0087 0.0098 0.0110 a 2 0.290 0.300 0.310 0.0114 0.0118 0.0122 b 0.297 0.330 0.363 0.0116 0.0129 0.0143 b1 0.250 0.0098 e 0.500 0.0197 s 0.210 0.230 0.250 0.0082 0.0090 0.0098 d 0.920 0.960 1.000 0.0362 0.0378 0.0394 e 1.420 1.460 1.500 0.0559 0.0575 0.0591 k 0.028 0.065 0.102 0.0011 0.0025 0.0040 ecn: t15-0140-rev. a, 20-apr-15 dwg: 6035 d e s a a1 a2 s e e s s xxxx xxx mark on backside of die e e e e d d s g s s note 5 abc recommended land pattern 6x ? b1 bump (note 2) k b 6x ? 0.24 to 0.26 (note 3) solder mask ~ ? 0.25
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